Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results

摘要

Debugging is a time-consuming task. This holds especially for large programs that are usually written by different groups of programmers. An example for this observation is the hardware design domain. Nowadays hardware designs are written in special hardware description language, e.g., VHDL, by groups which work in different companies and places. Moreover, there is a high pressure for completing the system in time with a very high quality because of the huge costs for correcting a bug after manufacturing the circuit. In order to decrease time for debugging we introduce an approach for diagnosis of VHDL hardware designs and present first empirical results. In contrast to other debugging approaches we make use of model-based diagnosis which is a general diagnosis approach. The models we use are logical descriptions of the syntax and semantics of a VHDL program that can be automatically derived from the program at compile time. The main part of this paper describes a general model and the derivation of specialized models that capture only some aspects of the program. The specialized models should be used in a specific debugging situation where they deliver the most appropriate solution in reasonable time. In order to select such a model we propose the use of a probability-based selection strategy. For example, larger programs should be debugged using a model only distinguishing concurrent VHDL statements and not sequential statements. As a result of multi-model reasoning in this domain we expect performance gains allowing to debug larger designs in a reasonable time, and more expressive diagnosis results.