Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip
作者：
Highlights：
• We introduce a novel modeling framework for fault-tolerant VLSI circuits.
• We cast a self-stabilizing clocking scheme from a companion article in this model.
• We discuss the implications of theory and model for the resulting implementation.
• We present the measures taken to avoid metastable upsets despite faults.
• We provide experimental data from a prototype FPGA implementation of the algorithm.
摘要
•We introduce a novel modeling framework for fault-tolerant VLSI circuits.•We cast a self-stabilizing clocking scheme from a companion article in this model.•We discuss the implications of theory and model for the resulting implementation.•We present the measures taken to avoid metastable upsets despite faults.•We provide experimental data from a prototype FPGA implementation of the algorithm.
论文关键词：Modeling framework,Clock synchronization,Hardware implementation,Experiments,Metastability,Dependability,Theoretical analysis,Hybrid state machines,Byzantine fault-tolerance,Self-stabilization
论文评审过程：Received 23 January 2013, Revised 18 October 2013, Accepted 6 January 2014, Available online 15 January 2014.
论文官网地址：https://doi.org/10.1016/j.jcss.2014.01.001
