A parallel architecture for relaxation operations

摘要

Relaxation method attracts attention as an effective parallel method in image processing and pattern recognition. But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. Its effectiveness is discussed by evaluating its performance when applied to a pattern recognition method.