VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images.
A VLSI Parallel Architecture for Fuzzy Expert Systems.
Enpassant: An Environment for Evaluating Massively Parallel Array Architectures for Spatially Mapped Applications.
PMAC: A Polygon Matching Chip.
Systolic Merging and Ranking of Votes for the Generalized Hough Transform.
A Fast Pattern-Matching Algorithm on Modular Mesh-Connected Computers with Multiple Buses.
High-Speed Parallel VLSI Architectures for Image Decorrelation.
Quadtree Algorithms for Template Matching on Mesh Connected Computer.
A VLSI Implementation of the Inverse Discrete Cosine Transform.
A Design Methodology for Very Large Array Processors - Part 1: Gipop Processor Array.
A Reconfigurable Architecture for Image Processing and Computer Vision.
A Design Methodology for Very Large Array Processors - Part 2: Pacube VLSI Arrays.