TCAD - volume 37 - 2018 论文列表 |
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Volume 37, Number 12, December 2018
Wei-Che Wang Charles Zhao Puneet Gupta
Improved Synthesis of Compressor Trees in High-Level Synthesis for Modern FPGAs.Le Tu Yuelai Yuan Kan Huang Xiaoqiang Zhang Dihu Chen Zixin Wang
SAT-Based Fault Equivalence Checking in Functional Safety Verification.Ai Quoc Dao Mark Po-Hung Lin Alan Mishchenko
Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function.Jing Ye Qingli Guo Yu Hu Xiaowei Li
Testing 3D-SoCs Using 2-D Time-Division Multiplexing.Panagiotis Georgiou Fotis Vartziotis Xrysovalantis Kavousianos Krishnendu Chakrabarty
Provably Fast and Near-Optimum Gate Sizing.Siad Daboul Nicolai Hähnle Stephan Held Ulrike Schorr
A Data-Driven Verilog-A ReRAM Model.Ioannis Messaris Alexander Serb Spyros Stathopoulos Ali Khiat Spyridon Nikolaidis Themistoklis Prodromakis
Fast Electromigration Immortality Analysis for Multisegment Copper Interconnect Wires.Zeyu Sun Ertugrul Demircan Mehul D. Shroff Chase Cook Sheldon X.-D. Tan
The MTA: An Advanced and Versatile Thermal Simulator for Integrated Systems.Scott Ladenheim Yi-Chung Chen Milan Mihajlovic Vasilis F. Pavlidis
Stochastic Circuit Synthesis by Cube Assignment. Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs.Ibrahim Ahmed Shuze Zhao Olivier Trescases Vaughn Betz
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.Leibo Liu Bo Wang Chenchen Deng Min Zhu Shouyi Yin Shaojun Wei
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning.Pai-Yu Chen Xiaochen Peng Shimeng Yu
An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding.Aidyn Zhakatayev Kyounghoon Kim Kiyoung Choi Jongeun Lee
AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips.Kailin Yang Hailong Yao Tsung-Yi Ho Kunze Xin Yici Cai
An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata.Frank Sill Torres Robert Wille Philipp Niemann Rolf Drechsler
Hardware Protection via Logic Locking Test Points.Michael Chen Elham K. Moghaddam Nilanjan Mukherjee Janusz Rajski Jerzy Tyszer Justyna Zawada
Leak Point Locating in Hardware Implementations of Higher-Order Masking Schemes.Ming Tang Yanbin Li Dongyan Zhao Yuguang Li Fei Yan Huanguo Zhang
Exploiting Oscillator Arrays As Randomness Sources for Cryptographic Applications. Efficient Hierarchical Performance Modeling for Analog and Mixed-Signal Circuits via Bayesian Co-Learning.Mohamed Baker Alawieh Fa Wang Xin Li
Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions.Farshad Firouzi Bahar J. Farahani Mohamed Ibrahim Krishnendu Chakrabarty
Volume 37, Number 11, November 2018
Hyesun Hong Hanwoong Jung KangKyu Park Soonhoi Ha
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference.Francesco Conti Pasquale Davide Schiavone Luca Benini
Weighted Quantization-Regularization in DNNs for Weight Memory Minimization Toward HW Implementation.Matthias Wess Sai Manoj Pudukotai Dinakarrao Axel Jantsch
WARD: Wear Aware RAID Design Within SSDs.Shunzhuo Wang Fei Wu Zhonghai Lu Jiaona Zhou Changsheng Xie
Using Control Synthesis to Generate Corner Cases: A Case Study on Autonomous Driving.Glen Chou Yunus Emre Sahin Liren Yang Kwesi J. Rutledge Petter Nilsson Necmiye Ozay
Two-Layered Falsification of Hybrid Systems Guided by Monte Carlo Tree Search.Zhenya Zhang Gidon Ernst Sean Sedwards Paolo Arcaini Ichiro Hasuo
Trading-Off Accuracy and Energy of Deep Inference on Embedded Systems: A Co-Design Approach.Nitthilan Kannappan Jayakodi Anwesha Chatterjee Wonje Choi Janardhan Rao Doppa Partha Pratim Pande
Towards Overhead-Free Interface Theory for Compositional Hierarchical Real-Time Systems.Jin Hyun Kim Kyong Hoon Kim Arvind Easwaran Insup Lee
Thermal-Aware Resource Management for Embedded Real-Time Systems.Youngmoon Lee Hoon Sung Chwa Kang G. Shin Shige Wang
The Opacity of Real-Time Automata.Lingtai Wang Naijun Zhan Jie An
Synthesizable Higher-Order Functions for C++.Dustin Richmond Alric Althoff Ryan Kastner
Synthesis of Monitors for Networked Systems With Heterogeneous Safety Requirements.Mischa Möstl Johannes Schlatow Rolf Ernst
Symbolic Verification of Cache Side-Channel Freedom.Sudipta Chattopadhyay Abhik Roychoudhury
SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling. Scrubbing-Aware Secure Deletion for 3-D NAND Flash.Wei-Chen Wang Chien-Chung Ho Yuan-Hao Chang Tei-Wei Kuo Ping-Hsien Lin
Scratch That (But Cache This): A Hybrid Register Cache/Scratchpad for GPUs.Jonathan Bailey John Kloosterman Scott A. Mahlke
Safety Verification of Nonlinear Hybrid Systems Based on Bilinear Programming.Yifan Zhang Zhengfeng Yang Wang Lin Huibiao Zhu Xin Chen Xuandong Li
Resource Optimization for Real-Time Streaming Applications Using Task Replication.Sobhan Niknam Peng Wang Todor P. Stefanov
Real-Time Data Retrieval With Multiple Availability Intervals in CPS Under Freshness Constraints.Chenchen Fu Peng Wu Minming Li Chun Jason Xue Yingchao Zhao Song Han
Priority Neuron: A Resource-Aware Neural Network for Cyber-Physical Systems. Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores.Mohammad Shihabul Haque Arvind Easwaran
Power- and Endurance-Aware Neural Network Training in NVM-Based Platforms.Fanruo Meng Yuan Xue Chengmo Yang
Parametric Critical Path Analysis for Event Networks With Minimal and Maximal Time Lags.Joost van Pinxten Marc Geilen Martijn Hendriks Twan Basten
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators.Luca Piccolboni Giuseppe Di Guglielmo Luca P. Carloni
Optimizing Graph Algorithms in Asymmetric Multicore Processors.Jyothi Krishna V. S Rupesh Nasre
NVM-Based FPGA Block RAM With Adaptive SLC-MLC Conversion.Lei Ju Xiaojin Sui Shiqing Li Mengying Zhao Chun Jason Xue Jingtong Hu Zhiping Jia
Moore-Machine Filtering for Timed and Untimed Pattern Matching. Modeling, Analysis, and Hard Real-Time Scheduling of Adaptive Streaming Applications.Jiali Teddy Zhai Sobhan Niknam Todor P. Stefanov
Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication.Hassaan Saadat Haseeb Bokhari Sri Parameswaran
McDRAM: Low Latency and Energy-Efficient Matrix Computations in DRAM.Hyunsung Shin Dongyoung Kim Eunhyeok Park Sungho Park Yongsik Park Sungjoo Yoo
MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip.Lei Gong Chao Wang Xi Li Huaping Chen Xuehai Zhou
Lightweight, Integrated Data Deduplication for Write Stress Reduction of Mobile Flash Storage.Miao-Chiang Yen Shih-Yi Chang Li-Pin Chang
Improving and Estimating the Precision of Bounds on the Worst-Case Latency of Task Chains.Alain Girault Christophe Prévot Sophie Quinton Rafik Henia Nicolas Sordon
Hot-Spot Suppression for Resource-Constrained Image Recognition Devices With Nonvolatile Memory.Chun-Feng Wu Ming-Chang Yang Yuan-Hao Chang Tei-Wei Kuo
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis.Tingyuan Liang Jieru Zhao Liang Feng Sharad Sinha Wei Zhang
Heterogeneous FPGA-Based Cost-Optimal Design for Timing-Constrained CNNs.Weiwen Jiang Edwin Hsing-Mean Sha Qingfeng Zhuge Lei Yang Xianzhang Chen Jingtong Hu
Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines.Siting Liu Honglan Jiang Leibo Liu Jie Han
GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration.Jiale Yan Shouyi Yin Fengbin Tu Leibo Liu Shaojun Wei
GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow.Seaghan Sefton Taiman Siddiqui Nathaniel St. Amour Gordon Stewart Avinash Karanth Kodi
Frequency Scaling As a Security Threat on Multicore Systems.Philipp Miedl Xiaoxi He Matthias Meyer Davide Basilio Bartolini Lothar Thiele
Formal Modeling and Verification of Controllers for a Family of DRAM Caches.Debiprasanna Sahoo Swaraj Sha Manoranjan Satpathy Madhu Mutyam S. Ramesh Partha S. Roop
Formal Feature Interpretation of Hybrid Systems.Antonio Anastasio Bruto da Costa Goran Frehse Pallab Dasgupta
Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice.Georgios Mappouras Alireza Vahid A. Robert Calderbank Daniel J. Sorin
EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems.Jordi Cardona Carles Hernández Jaume Abella Francisco J. Cazorla
ENZYME: An Energy-Efficient Transient Computing Paradigm for Ultralow Self-Powered IoT Edge Devices. Energy-Quality-Time Optimized Task Mapping on DVFS-Enabled Multicores.Lei Mo Angeliki Kritikakou Olivier Sentieys
Energy Management of Applications With Varying Resource Usage on Smartphones.Anway Mukherjee Thidapat Chantem
End-to-End Analysis and Design of a Drone Flight Controller.Zhuoqun Cheng Richard West Craig Einstein
EDF-VD Scheduling of Flexible Mixed-Criticality System With Multiple-Shot Transitions.Gang Chen Nan Guan Biao Hu Wang Yi
Discrete Choice in the Presence of Numerical Uncertainties.Debasmita Lohar Eva Darulova Sylvie Putot Eric Goubault
Digital Foveation: An Energy-Aware Machine Vision Framework.Ekdeep Singh Lubana Robert P. Dick
DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks.Duckhwan Kim Taesik Na Sudhakar Yalamanchili Saibal Mukhopadhyay
DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters.Zhuoran Zhao Kamyar Mirzazad Barijough Andreas Gerstlauer
Co-Scheduling on Fused CPU-GPU Architectures With Shared Last Level Caches.Marvin Damschen Frank Mueller Jörg Henkel
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems.Mohamed Hassan Rodolfo Pellizzoni
Automatic Verification of Embedded System Code Manipulating Dynamic Structures Stored in Contiguous Regions.Jiangchao Liu Liqian Chen Xavier Rival
Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators.Inpyo Bae Barend Harris Hyemi Min Bernhard Egger
ASSURED: Architecture for Secure Software Update of Realistic Embedded Devices.N. Asokan Thomas Nyman Norrathep Rattanavipanon Ahmad-Reza Sadeghi Gene Tsudik
Architecture Considerations for Stochastic Computing Accelerators.Vincent T. Lee Armin Alaghi Rajesh Pamula Visvesh S. Sathe Luis Ceze Mark Oskin
Approximate Computing for Long Short Term Memory (LSTM) Neural Networks.Sanchari Sen Anand Raghunathan
Analyzing Data Cache Related Preemption Delay With Multiple Preemptions.Wei Zhang Nan Guan Lei Ju Weichen Liu
Analytical Characterization of End-to-End Communication Delays With Logical Execution Time.Jorge Martinez Ignacio Sanudo Olmedo Marko Bertogna
An Algebraic Framework for Runtime Verification.Stefan Jaksic Ezio Bartocci Radu Grosu Dejan Nickovic
A Failure Recovery Protocol for Software-Defined Real-Time Networks. A Design Space Exploration Framework for Convolutional Neural Networks Implemented on Edge Devices.Foivos Tsimpourlas Lazaros Papadopoulos Anastasios Bartsokas Dimitrios Soudris
A Capacity Augmentation Bound for Real-Time Constrained-Deadline Parallel Tasks Under GEDF.Jinghao Sun Nan Guan Xu Jiang Shuangshuang Chang Zhishan Guo Qingxu Deng Wang Yi
A Unified Framework for Period and Priority Optimization in Distributed Hard Real-Time Systems. Editorial.Volume 37, Number 10, October 2018
Paolo Maffezzoni Zheng Zhang Salvatore Levantino Luca Daniel
On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug.Yun Cheng Huawei Li Ying Wang Haihua Shen Bo Liu Xiaowei Li
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits.Jan Burchard Dominik Erb Sudhakar M. Reddy Adit D. Singh Bernd Becker
A Model-Based-Random-Forest Framework for Predicting Vt Mean and Variance Based on Parallel Id Measurement.Chien-Hsueh Lin Chih-Ying Tsai Kao-Chi Lee Sung-Chu Yu Wen-Rong Liau Alex Chun-Liang Hou Ying-Yen Chen Chun-Yi Kuo Jih-Nung Lee Mango C.-T. Chao
Adaptive Test With Test Escape Estimation for Mixed-Signal ICs.Haralampos-G. D. Stratigopoulos Christian Streitwieser
Toward Predictive Fault Tolerance in a Core-Router System: Anomaly Detection Using Correlation-Based Time-Series Analysis.Shi Jin Zhaobo Zhang Krishnendu Chakrabarty Xinli Gu
Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops.Arunkumar Vijayan Saman Kiamehr Fabian Oboril Krishnendu Chakrabarty Mehdi Baradaran Tahoori
Circuit and Methodology for Testing Small Delay Faults in the Clock Network.Shaofu Yang Zhi-Yuan Wen Shi-Yu Huang Kun-Han Tsai Wu-Tung Cheng
Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors.Haoran Li Jiang Xu Zhe Wang Rafael K. V. Maeda Peng Yang Zhongyuan Tian
Profit: Priority and Power/Performance Optimization for Many-Core Systems.Zhuo Chen Dimitrios Stamoulis Diana Marculescu
Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice.Maxime Pelcat Alexandre Mercat Karol Desnos Luca Maggiani Yanzhou Liu Julien Heulot Jean-François Nezan Wassim Hamidouche Daniel Ménard Shuvra S. Bhattacharyya
CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design.Jian Kuang Evangeline F. Y. Young Bei Yu
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.Gengjie Chen Chak-Wa Pui Wing-Kai Chow Ka-Chun Lam Jian Kuang Evangeline F. Y. Young Bei Yu
Capacitance Extraction With Provably Good Absorbing Boundary Conditions.Yuhan Zhou Robert D. Nevels Weiping Shi
Density-Uniformity-Aware Analog Layout Retargeting.Gholamreza Shomalnasab Lihong Zhang
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.Zihao Liu Mengjie Mao Tao Liu Xue Wang Wujie Wen Yiran Chen Hai Li Danghui Wang Yukui Pei Ning Ge
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators.Ying Wang Huawei Li Xiaowei Li
ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs.Jinhua Cui Youtao Zhang Liang Shi Chun Jason Xue Weiguo Wu Jun Yang
InnovA: A Cognitive Architecture for Computational Innovation Through Robust Divergence and Its Application for Analog Circuit Design.Hao Li Xiaowei Liu Fanshu Jiao Alex Doboli Simona Doboli
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.Mengshuo Wang Wenlong Lv Fan Yang Changhao Yan Wei Cai Dian Zhou Xuan Zeng
Modeling and Extraction of Causal Information in Analog Circuits.Volume 37, Number 9, September 2018
Muhammad Adil Ansari Jihun Jung Dooyoung Kim Sungju Park
Fast Algebraic Rewriting Based on And-Inverter Graphs.Cunxi Yu Maciej J. Ciesielski Alan Mishchenko
Failure Triage in RTL Regression Verification.Zissis Poulos Andreas G. Veneris
Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads. Secure Scan and Test Using Obfuscation Throughout Supply Chain.Xiaoxiao Wang Dongrong Zhang Miao Tony He Donglin Su Mark M. Tehranipoor
Vertical Arbitration-Free 3-D NoCs.Ankit More Vasil Pano Baris Taskin
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).Eric Cheng Shahrzad Mirkhani Lukasz G. Szafaryn Chen-Yong Cher Hyungmin Cho Kevin Skadron Mircea R. Stan Klas Lilja Jacob A. Abraham Pradip Bose Subhasish Mitra
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing.Jinwook Jung Gi-Joon Nam Lakshmi N. Reddy Iris Hui-Ru Jiang Youngsoo Shin
Reliable Hybrid Small-Signal Modeling of GaN HEMTs Based on Particle-Swarm-Optimization.Ahmed S. Hussein Anwar Jarndal
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis.Junyi Liu John Wickerson Samuel Bayliss George A. Constantinides
Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption.Shaahin Angizi Zhezhi He Nader Bagherzadeh Deliang Fan
Image Edge Detection Based on Swarm Intelligence Using Memristive Networks. DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance.Ishan G. Thakkar Sudeep Pasricha
Nonvolatile Write Buffer-Based Journaling Bypass for Storage Write Reduction in Mobile Devices.Mungyu Son Junwhan Ahn Sungjoo Yoo
Cost-Constrained QoS Optimization for Approximate Computation Real-Time Tasks in Heterogeneous MPSoCs.Tongquan Wei Junlong Zhou Kun Cao Peijin Cong Mingsong Chen Gongxuan Zhang Xiaobo Sharon Hu Jianming Yan
Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design.Baolei Mao Wei Hu Alric Althoff Janarbek Matai Yu Tai Dejun Mu Timothy Sherwood Ryan Kastner
Volume 37, Number 8, August 2018
Wenjian Yu Zhezhao Xu Bo Li Cheng Zhuo
A Runtime Optimization Approach for FPGA Routing.Dekui Wang Zhenhua Duan Cong Tian Bohu Huang Nan Zhang
Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification.Pramod Subramanyan Bo-Yuan Huang Yakir Vizel Aarti Gupta Sharad Malik
Time-Multiplexed 1687-Network for Test Cost Reduction.Muhammad Adil Ansari Jihun Jung Dooyoung Kim Sungju Park
Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers.Ali Pahlevan Xiaoyu Qu Marina Zapater David Atienza
On-Chip Optical Channel Routing for Signal Loss Minimization. A Novel Approach for Using TSVs As Membrane Capacitance in Neuromorphic 3-D IC.M. Amimul Ehsan Hongyu An Zhen Zhou Yang Yi
Leakage Models for High-Level Power Estimation.Domenik Helms Reef Eilers Malte Metzdorf Wolfgang Nebel
Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits. PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits.Mohammad Ansari Arash Fayyazi Ali BanaGozar Mohammad Ali Maleki Mehdi Kamal Ali Afzali-Kusha Massoud Pedram
Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips.Tsun-Ming Tseng Mengchu Li Daniel Nestor Freitas Travis McAuley Bing Li Tsung-Yi Ho Ismail Emre Araci Ulf Schlichtmann
Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.Yibo Lin Bei Yu Meng Li David Z. Pan
Optimizing Cache Bypassing and Warp Scheduling for GPUs.Yun Liang Xiaolong Xie Yu Wang Guangyu Sun Tao Wang
DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems.Jinhua Cui Youtao Zhang Weiguo Wu Jun Yang Yinfeng Wang Jianhang Huang
TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip.Arman Iranfar Mehdi Kamal Ali Afzali-Kusha Massoud Pedram David Atienza
The Promise and Challenge of Stochastic Computing.Volume 37, Number 7, July 2018
Jea Woo Park Andres Torres Xiaoyu Song
A Compact Scheme of Reading and Writing for Memristor-Based Multivalued Memory.Xiaoping Wang Shuai Li Hui Liu Zhigang Zeng
An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines. Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits.Xiaofeng Tang Aiqiang Xu Ruifeng Li Min Zhu Jinling Dai
Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis.Hayoung Lee Kiwon Cho Donghyun Kim Sungho Kang
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility.Alex Kahng Andrew B. Kahng Hyein Lee Jiajia Li
Numerical Analysis of Multidomain Systems: Coupled Nonlinear PDEs and DAEs With Noise. A Novel Design for Memristor-Based Multiplexer Via NOT-Material Implication.Xiaoping Wang Qian Wu Qiao Chen Zhigang Zeng
Logic Synthesis for RRAM-Based In-Memory Computing.Saeideh Shirinzadeh Mathias Soeken Pierre-Emmanuel Gaillardon Rolf Drechsler
Lorenz Chaotic System-Based Carbon Nanotube Physical Unclonable Functions. VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.Sarath Mohanachandran Nair Rajendra Bishnoi Mohammad Saber Golanbari Fabian Oboril Fazal Hameed Mehdi Baradaran Tahoori
Potential Trigger Detection for Hardware Trojans.Minhui Zou Xiaotong Cui Liang Shi Kaijie Wu
Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis.Xiaoming Chen Qiaoyi Liu Song Yao Jia Wang Qiang Xu Yu Wang Yongpan Liu Huazhong Yang
Control Flow Integrity Based on Lightweight Encryption Architecture.Pengfei Qiu Yongqiang Lyu Jiliang Zhang Dongsheng Wang Gang Qu
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories.Daniele Rossi Vasileios Tenentes Sudhakar M. Reddy Bashir M. Al-Hashimi Andrew Brown
CNFET-Based High Throughput SIMD Architecture.Li Jiang Tianjian Li Naifeng Jing Nam Sung Kim Minyi Guo Xiaoyao Liang
Power Grid Electromigration Checking Using Physics-Based Models.Volume 37, Number 6, June 2018
Michael Shoniker Oleg Oleynikov Bruce F. Cockburn Jie Han Manish Rana Witold Pedrycz
Methodologies for Diagnosis of Unreachable States via Property Directed Reachability.Ryan Berryhill Andreas G. Veneris
Improving Diagnostic Resolution of Failing ICs Through Learning.Yang Xue Xin Li Ronald D. Blanton
Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points. A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors.Ying Wang Huawei Li Yinhe Han Xiaowei Li
STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning.Jian Kuang Junjie Ye Evangeline F. Y. Young
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.Yibo Lin Bei Yu Xiaoqing Xu Jhih-Rong Gao Natarajan Viswanathan Wen-Hao Liu Zhuo Li Charles J. Alpert David Z. Pan
Subresolution Assist Feature Generation With Supervised Data Learning.Xiaoqing Xu Yibo Lin Meng Li Tetsuaki Matsunawa Shigeki Nojima Chikaaki Kodama Toshiya Kotani David Z. Pan
QIG: Quantifying the Importance and Interaction of GPGPU Architecture Parameters.Zhibin Yu Jing Wang Lieven Eeckhout Chengzhong Xu
Area Optimization of Timing Resilient Designs Using Resynthesis.Hsin-Ho Huang Huimei Cheng Chris Chu Peter A. Beerel
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM.Infall Syafalni Tsutomu Sasao Xiaoqing Wen
CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance.Leibo Liu Chen Yang Shouyi Yin Shaojun Wei
Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips.Qin Wang Hao Zou Hailong Yao Tsung-Yi Ho Robert Wille Yici Cai
Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition.Olga Krestinskaya Timur Ibrayev Alex Pappachen James
Sensor-Based Time Speculation in the Presence of Timing Variability.Chung-Han Chou Tsui-Yun Chang Kai-Chiang Wu Shih-Chieh Chang
Secure Randomized Checkpointing for Digital Microfluidic Biochips.Jack Tang Mohamed Ibrahim Krishnendu Chakrabarty Ramesh Karri
Volume 37, Number 5, May 2018
Yansong Gao Hua Ma Said F. Al-Sarawi Derek Abbott Damith Chinthana Ranasinghe
On Probability of Detection Lossless Concurrent Error Detection Based on Implications. Bit-Flip Detection-Driven Selection of Trace Signals. Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress.Arunkumar Vijayan Abhishek Koneru Saman Kiamehr Krishnendu Chakrabarty Mehdi Baradaran Tahoori
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs. Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation.Mohammad Nazmus Sakib Rakibul Hassan Satyendra N. Biswas Sunil R. Das
A Simple and Effective Heuristic Method for Threshold Logic Identification.Augusto Neutzling Mayler G. A. Martins Vinicius Callegaro André Inácio Reis Renato P. Ribas
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.Lixue Xia Boxun Li Tianqi Tang Peng Gu Pai-Yu Chen Shimeng Yu Yu Cao Yu Wang Yuan Xie Huazhong Yang
One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic. Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing.Giuseppe Tagliavini Davide Rossi Andrea Marongiu Luca Benini
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.Zipeng Li Kelvin Yi-Tse Lai Po-Hsien Yu Krishnendu Chakrabarty Tsung-Yi Ho Chen-Yi Lee
Exact Interference of Tasks With Variable Rate-Dependent Behavior. Chip Temperature Optimization for Dark Silicon Many-Core Systems.Mengquan Li Weichen Liu Lei Yang Peng Chen Chao Chen
SD-PUF: Spliced Digital Physical Unclonable Function. HDL-Based Synthesis System With Debugger for Current-Mode FPAA.Volume 37, Number 4, April 2018
Jaeil Lim Hyunggoy Oh Heetae Kim Sungho Kang
Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA.Anita Aghaie Mehran Mozaffari Kermani Reza Azarderakhsh
New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications.Jiajia Chen Chip-Hong Chang Yujia Wang Juan Zhao Susanto Rahardja
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs.Vasileios Tenentes Daniele Rossi S. Saqib Khursheed Bashir M. Al-Hashimi Krishnendu Chakrabarty
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing.Wuxi Li Shounak Dhar David Z. Pan
Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes.Sorin Dobre Andrew B. Kahng Jiajia Li
Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs.Sheng-En David Lin Dae Hyun Kim
Identifying Wafer-Level Systematic Failure Patterns via Unsupervised Learning.Mohamed Baker Alawieh Fa Wang Xin Li
Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors.Morteza Gholipour Ying-Yu Chen Deming Chen
Classifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPs.Mohammadreza Soltaniyeh Ismail Kadayif Ozcan Ozturk
High-Performance Architecture for Binary-Tree-Based Finite State Machines.Raouf Senhadji-Navarro Ignacio Garcia-Vargas
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures.Leibo Liu Zhuoquan Zhou Shaojun Wei Min Zhu Shouyi Yin Shengyang Mao
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning.Hengliang Zhu Feng Hu Hao Zhou David Z. Pan Dian Zhou Xuan Zeng
An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache.Cheng Ji Li-Pin Chang Chao Wu Liang Shi Chun Jason Xue
Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis.Anirban Sengupta Dipanjan Roy Saraju P. Mohanty
Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics.Xiaowei Xu Feng Lin Aosen Wang Xin-Wei Yao Qing Lu Wenyao Xu Yiyu Shi Yu Hu
Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC.Tao-Chun Yu Shao-Yun Fang Chia-Ching Chen Yulong Sun Poki Chen
Volume 37, Number 3, March 2018
Konrad Möller Martin Kumm Mario Garrido Peter Zipf
Composable Worst-Case Delay Bound Analysis Using Network Calculus.Yanchen Long Zhonghai Lu Haibin Shen
Reliable Inversion in GF(28) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures.Mehran Mozaffari Kermani Amir Jalali Reza Azarderakhsh Jiafeng Xie Kim-Kwang Raymond Choo
Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures.Travis Boraten Avinash Karanth Kodi
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.Chau-Chin Huang Hsin-Ying Lee Bo-Qiao Lin Sheng-Wei Yang Chin-Hao Chang Szu-To Chen Yao-Wen Chang Tung-Chieh Chen Ismail Bustany
Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration.Yixiao Ding Chris Chu Wai-Kei Mak
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling.Marco Donato R. Iris Bahar William R. Patterson Alexander Zaslavsky
How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance.Dries Vercruyce Elias Vansteenkiste Dirk Stroobandt
Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip.Wajid Hassan Minhass Jeffrey McDaniel Michael Lander Raagaard Philip Brisk Paul Pop Jan Madsen
Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip.Zipeng Li Kelvin Yi-Tse Lai John McCrone Po-Hsien Yu Krishnendu Chakrabarty Miroslav Pajic Tsung-Yi Ho Chen-Yi Lee
Detection and Diagnosis of Single Faults in Quantum Circuits. Combating Coordinated Pricing Cyberattack and Energy Theft in Smart Home Cyber-Physical Systems.Yang Liu Yuchen Zhou Shiyan Hu
Insertion Loss-Aware Routing Analysis and Optimization for a Fat-Tree-Based Optical Network-on-Chip.Jae Hoon Lee Min Soo Kim Tae Hee Han
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing.Yoon Seok Yang Hrishikesh Deshpande Gwan Choi Paul V. Gratz
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.Yishi Yang Hengliang Zhu Zhaori Bi Changhao Yan Dian Zhou Yangfeng Su Xuan Zeng
Accelerated and Reliable Analog Circuits Yield Analysis Using SMT Solving Techniques.Volume 37, Number 2, February 2018
Arunkumar Vijayan Saman Kiamehr Mojtaba Ebrahimi Krishnendu Chakrabarty Mehdi Baradaran Tahoori
Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications.Tong-Yu Hsieh Yi-Han Peng Kuan-Chih Cheng
Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism. TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion.Kyuseung Han Jae-Jin Lee Jinho Lee Woojoo Lee Massoud Pedram
Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning.Byunghoon Lee Kwangsu Kim Eui-Young Chung
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays.Shouyi Yin Zhicong Xie Chenyue Meng Peng Ouyang Leibo Liu Shaojun Wei
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators.Andrey Ayupov Serif Yesil Muhammet Mustafa Ozdal Taemin Kim Steven M. Burns Ozcan Ozturk
Global Routing With Timing Constraints.Stephan Held Dirk Müller Daniel Rotter Rudolf Scheifele Vera Traub Jens Vygen
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning.Grace Li Zhang Bing Li Jinglan Liu Yiyu Shi Ulf Schlichtmann
Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms.Michele Lora Sara Vinco Enrico Fraccaroli Davide Quaglia Franco Fummi
xMAS-Based QoS Analysis Methodology. Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms.Hao Liang Sharad Sinha Wei Zhang
Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays.Insik Yoon Arijit Raychowdhury
A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits.A. N. Nagamani S. N. Anuktha N. Nanditha Vinod Kumar Agrawal
A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar.Lei Xie Hoang Anh Du Nguyen Mottaqiallah Taouil Said Hamdioui Koen Bertels
Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures.Tobias Schwarzer Andreas Weichslgartner Michael Glaß Stefan Wildermann Peter Brand Jürgen Teich
A Single Layer 3-D Touch Sensing System for Mobile Devices Application.Li Du Chun-Chen Liu Yan Zhang Yilei Li Yuan Du Yen-Cheng Kuan Mau-Chung Frank Chang
Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation.Volume 37, Number 1, January 2018
Dara Rahmati Hamid Sarbazi-Azad
Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint.Taehee Lee David Z. Pan Joon-Sung Yang
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations.Derong Liu Bei Yu Salim Chowdhury David Z. Pan
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques.Xiaotao Jia Yici Cai Qiang Zhou Bei Yu
Exact Timing Analysis for Asynchronous Systems. Design of Application-Specific Architectures for Networked Labs-on-Chips.Andreas Grimmer Werner Haselmayr Andreas Springer Robert Wille
A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit.Abhoy Kole Kamalika Datta Indranil Sengupta
Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives.Congming Gao Liang Shi Cheng Ji Yejia Di Kaijie Wu Chun Jason Xue Edwin Hsing-Mean Sha
A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags.Weiwei Shi An Pan Shi Yu Chiu-sing Choy
A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications.Yilei Li Kirti Dhwaj Chien-Heng Wong Yuan Du Li Du Yiwu Tang Yiyu Shi Tatsuo Itoh Mau-Chung Frank Chang
Toward Smart Building Design Automation: Extensible CAD Framework for Indoor Localization Systems Deployment.Andrea Cirigliano Roberto Cordone Alessandro Antonio Nacci Marco Domenico Santambrogio
On Random Dynamic Voltage Scaling for Internet-of-Things: A Game-Theoretic Approach.Hui Geng Kevin A. Kwiat Charles A. Kamhoua Yiyu Shi
FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices.S. Dinesh Kumar Himanshu Thapliyal Azhar Mohammad
Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF.Cédric Marchand Lilian Bossuet Ugo Mureddu Nathalie Bochard Abdelkarim Cherkaoui Viktor Fischer
Enabling Security-Enhanced Attestation With Intel SGX for Remote Terminal and IoT.Juan Wang Zhi Hong Yuhan Zhang Yier Jin
qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses.Shaoming Chen Lu Peng Samuel Irving Zhou Zhao Weihua Zhang Ashok Srivastava
High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds.Jonathan Beaumont Andrey Mokhov Danil Sokolov Alex Yakovlev
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration.Renzo Andri Lukas Cavigelli Davide Rossi Luca Benini
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA.Kaiyuan Guo Lingzhi Sui Jiantao Qiu Jincheng Yu Junbin Wang Song Yao Song Han Yu Wang Huazhong Yang
Multicore Mixed-Criticality Systems: Partitioned Scheduling and Utilization Bound.Jian-Jun Han Xin Tao Dakai Zhu Hakan Aydin Zili Shao Laurence T. Yang
Microprocessor Optimizations for the Internet of Things: A Survey.Tosiron Adegbija Anita Rogacs Chandrakant Patel Ann Gordon-Ross
Guest Editorial Circuit and System Design Automation for Internet of Things.Saraju P. Mohanty Michael Hübner Chun Jason Xue Xin Li Hai Li
Editorial.