Volume 38, Number 12, December 2019
Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences.

Irith Pomeranz

Predicting X-Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning Approach.

Manjari Pradhan Bhaswar B. Bhattacharya Krishnendu Chakrabarty Bhargab B. Bhattacharya

ARBSA: Adaptive Range-Based Simulated Annealing for FPGA Placement.

Junqi Yuan Jialing Chen Lingli Wang Xuegong Zhou Yinshui Xia Jianping Hu

Multi-Pair Active Shielding for Security IC Protection.

Kan Wang Yong Gu Tong Zhou Hao Chen

Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory.

Meng Zhang Fei Wu Yajuan Du Weihua Liu Changsheng Xie

Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach.

Yuzhe Ma Subhendu Roy Jin Miao Jiamin Chen Bei Yu

Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments.

Chin-Heng Liu Chia-Chun Lin Yung-Chih Chen Chia-Cheng Wu Chun-Yao Wang Shigeru Yamashita

Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning.

Dajiang Liu Shouyi Yin Guojie Luo Jiaxing Shang Leibo Liu Shaojun Wei Yong Feng Shangbo Zhou

Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening.

Mohamed Ibrahim Aditya Sridhar Krishnendu Chakrabarty Ulf Schlichtmann

Alleviating Hot Data Write Back Effect for Shingled Magnetic Recording Storage Systems.

Chenlin Ma Zhaoyan Shen Yi Wang Zili Shao

Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations.

Armin Haj Aboutalebi Ethan C. Ahn Bo Mao Suzhen Wu Lide Duan

Resource Management for Improving Soft-Error and Lifetime Reliability of Real-Time MPSoCs.

Junlong Zhou Jin Sun Xiumin Zhou Tongquan Wei Mingsong Chen Shiyan Hu Xiaobo Sharon Hu

DCR: Deterministic Crash Recovery for NAND Flash Storage Systems.

Renhai Chen Chi Zhang Yi Wang Zhaoyan Shen Duo Liu Zili Shao Yong Guan

Comprehensive Side-Channel Power Analysis of XTS-AES.

Chao Luo Yunsi Fei Aidong Adam Ding Pau Closas

A Millimeter Wave Loss-Aware Methodology for Switchless PALNA Integrated Circuit Design.

Iskren Abdomerovic Sanjay Raman


Volume 38, Number 11, November 2019
A Granular Resampling Method and Adaptive Speculative Mechanism-Based Energy-Efficient Architecture for Multiclass Heartbeat Classification.

Yin Xu Zhijian Chen Feiteng Li Jianyi Meng

Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems.

Yongshin Kang Joon-Sung Yang Jaeyong Chung

Spatial Timing Analysis With Exact Propagation of Delay and Application to FPGA Performance.

David M. Lewis Herman Schmit

Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC.

Yuxiang Fu Li Li Hongbing Pan Kun Wang Fan Feng Qinyu Chen Chuan Zhang

System-on-a-Chip (SoC)-Based Hardware Acceleration for an Online Sequential Extreme Learning Machine (OS-ELM).

Amin Safaei Q. M. Jonathan Wu Akilan Thangarajah Yimin Yang

A New Paradigm for FPGA Placement Without Explicit Packing.

Wuxi Li David Z. Pan

Single-Layer GNR Routing for Minimization of Bending Delay.

Jin-Tai Yan

An Efficient Extrapolation Method of Band-Limited S-Parameters for Extracting Causal Impulse Responses.

Jaeyong Cho Karam Hwang Seungil Jeung Seungyoung Ahn

Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks.

Chen Zhang Guangyu Sun Zhenman Fang Peipei Zhou Peichen Pan Jason Cong

STREAM: Stress and Thermal Aware Reliability Management for 3-D ICs.

Hai Wang Darong Huang Rui Liu Chi Zhang He Tang Yuan Yuan

Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms.

Qinghang Zhao Wenyu Sun Jiaqing Zhao Jian Zhao Hailong Yao Tsung-Yi Ho Xiaojun Guo Huazhong Yang Yongpan Liu

Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems.

Jaeyong Chung Taehwan Shin Joon-Sung Yang

Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors.

Zhiyuan Yang Caleb Serafy Tiantao Lu Ankur Srivastava

A Sufficient Response Time Analysis Considering Angular Phases Between Rate-Dependent Tasks.

Timo Feld Frank Slomka

A QoS-QoR Aware CNN Accelerator Design Approach.

Ying Wang Huawei Li Long Cheng Xiaowei Li

Obfuscated Built-In Self-Authentication With Secure and Efficient Wire-Lifting.

Qihang Shi Mark M. Tehranipoor Domenic Forte


Volume 38, Number 10, October 2019
Design Space Exploration of Neural Network Activation Function Circuits.

Tao Yang Yadong Wei Zhijun Tu Haolun Zeng Michel A. Kinsy Nanning Zheng Pengju Ren

Skewed-Load Tests for Transition and Stuck-at Faults.

Irith Pomeranz

Built-In Test for Hidden Delay Faults.

Matthias Kampmann Michael A. Kochte Chang Liu Eric Schneider Sybille Hellebrand Hans-Joachim Wunderlich

A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits.

Abhishek Koneru Sukeshwar Kannan Krishnendu Chakrabarty

Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield Enhancement.

Shengcheng Wang Krishnendu Chakrabarty Mehdi Baradaran Tahoori

A Cross-Layer Framework for Temporal Power and Supply Noise Prediction.

Yaguang Li Cheng Zhuo Pingqiang Zhou

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection.

Yibo Lin Meng Li Yuki Watanabe Taiki Kimura Tetsuaki Matsunawa Shigeki Nojima David Z. Pan

Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip.

Sudip Poddar Robert Wille Hafizur Rahaman Bhargab B. Bhattacharya

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW.

Simon Rokicki Erven Rohou Steven Derrien

Addressing Sparsity in Deep Neural Networks.

Xuda Zhou Zidong Du Shijin Zhang Lei Zhang Huiying Lan Shaoli Liu Ling Li Qi Guo Tianshi Chen Yunji Chen

Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods.

Xueyan Wang Qiang Zhou Yici Cai Gang Qu

Security Assessment of Micro-Electrode-Dot-Array Biochips.

Mohammed Shayan Jack Tang Krishnendu Chakrabarty Ramesh Karri

On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness.

Yumin Hou Hu He Kaveh Shamsi Yier Jin Dong Wu Huaqiang Wu

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT).

Yuan Du Li Du Xuefeng Gu Jieqiong Du X. Shawn Wang Boyu Hu Mingzhe Jiang Xiaoliang Chen Subramanian S. Iyer Mau-Chung Frank Chang

QoS-Adaptive Approximate Real-Time Computation for Mobility-Aware IoT Lifetime Optimization.

Kun Cao Guo Xu Junlong Zhou Tongquan Wei Mingsong Chen Shiyan Hu

Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams.

Carna Zivkovic Christoph Grimm Markus Olbrich Oliver Scharf Erich Barke


Volume 38, Number 9, September 2019
A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems.

Liang Wang Ping Lv Leibo Liu Jie Han Ho-fung Leung Xiaohang Wang Shouyi Yin Shaojun Wei Terrence S. T. Mak

TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods.

Woojoo Lee Taewook Kang Jae-Jin Lee Kyuseung Han Joongheon Kim Massoud Pedram

A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization.

Kai Huang Xiaomeng Zhang Dan-dan Zheng Min Yu Xiaowen Jiang Xiaolang Yan Lisane B. de Brisolara Ahmed Amine Jerraya

Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond.

Jian Kuang Evangeline F. Y. Young

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement.

Chung-Kuan Cheng Andrew B. Kahng Ilgweon Kang Lutong Wang

Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI.

Changho Han Andrew B. Kahng Lutong Wang Bangqi Xu

Optimal Performance-Aware Cooling on Enterprise Servers.

Christine S. Chan Alper Sinan Akyürek Baris Aksanli Tajana Simunic Rosing

LUT-Based Hierarchical Reversible Logic Synthesis.

Mathias Soeken Martin Roetteler Nathan Wiebe Giovanni De Micheli

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power.

Zhe Lin Sharad Sinha Wei Zhang

Design Automation of Meandered Interconnects for Stretchable Circuits.

Bart Plovie Jan Vanfleteren Thomas Vervust Andrés Vásquez Quintero Frederick Bossuyt

An Efficient LSM-Tree-Based SQLite-Like Database Engine for Mobile Devices.

Zhaoyan Shen Yuanjing Shi Zili Shao Yong Guan

New 3-D CMOS Fabric With Stacked Horizontal Nanowires.

Naveen Kumar Macha Md Arif Iqbal Mostafizur Rahman

Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems.

Lixue Xia Mengyun Liu Xuefei Ning Krishnendu Chakrabarty Yu Wang

Game Theoretic Feedback Control for Reliability Enhancement of EtherCAT-Based Networked Systems.

Liying Li Peijin Cong Kun Cao Junlong Zhou Tongquan Wei Mingsong Chen Shiyan Hu Xiaobo Sharon Hu

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.

Meng Li Bei Yu Yibo Lin Xiaoqing Xu Wuxi Li David Z. Pan


Volume 38, Number 8, August 2019
Taming the Stability-Constrained Performance Optimization Challenge of Distributed On-Chip Voltage Regulation.

Xin Zhan Peng Li Edgar Sánchez-Sinencio

Maestro: Autonomous QoS Management for Mobile Applications Under Thermal Constraints.

Onur Sahin Lothar Thiele Ayse K. Coskun

HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks.

Zhe Li Ji Li Ao Ren Ruizhe Cai Caiwen Ding Xuehai Qian Jeffrey Draper Bo Yuan Jian Tang Qinru Qiu Yanzhi Wang

Verification at RTL Using Separation of Design Concerns.

Maya H. Safieddine Fadi A. Zaraket Rouwaida Kanj Ali S. Elzein Wolfgang Roesner

On the Design of Time-Constrained and Buffer-Optimal Self-Timed Pipelines.

Weiwen Jiang Edwin Hsing-Mean Sha Qingfeng Zhuge Lei Yang Xianzhang Chen Jingtong Hu

Timing-Driven and Placement-Aware Multibit Register Composition.

Ioannis Seitanidis Giorgos Dimitrakopoulos Pavlos M. Mattheakis Laurent Masse-Navette David G. Chinnery

Table-Based Model of a Dual-Gate Transistor for Statistical Circuit Simulation.

Dominik Kasprowicz

A Versatile Pulse Control Method to Generate Arbitrary Multidirection Multibutterfly Chaotic Attractors.

Qinghui Hong Ya Li Xiaoping Wang Zhigang Zeng

Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems.

Stavros Hadjitheophanous Stelios N. Neophytou Maria K. Michael

ACHILLES: Accuracy-Aware High-Level Synthesis Considering Online Quality Management.

Shayan Tabatabaei Nikkhah Mahdi Zahedi Mehdi Kamal Ali Afzali-Kusha Massoud Pedram

ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors.

Hang Lu Yisong Chang Guihai Yan Ning Lin Xin Wei Xiaowei Li

Instruction-Level NBTI Stress Estimation and Its Application in Runtime Aging Prediction for Embedded Processors.

Iraj Moghaddasi Arash Fouman Mostafa E. Salehi Mehdi Kargahi

Energy-Aware Design of Stochastic Applications With Statistical Deadline and Reliability Guarantees.

Wei Jiang Xiong Pan Ke Jiang Liang Wen Qi Dong

Provably Secure Camouflaging Strategy for IC Protection.

Meng Li Kaveh Shamsi Travis Meade Zheng Zhao Bei Yu Yier Jin David Z. Pan

Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.

Jun Tao Yangfeng Su Dian Zhou Xuan Zeng Xin Li


Volume 38, Number 7, July 2019
Translation Validation of Code Motion Transformations Involving Loops.

Ramanuj Chouksey Chandan Karfa Purandar Bhaduri

A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs.

Liang Wang Xiaohang Wang Ho-fung Leung Terrence S. T. Mak

Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation.

Vladimir Herdt Hoang M. Le Daniel Große Rolf Drechsler

Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis.

Keith A. Campbell David Lin Leon He Liwei Yang Swathi T. Gurumani Kyle Rupnow Subhasish Mitra Deming Chen

Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a Core Router System.

Shi Jin Zhaobo Zhang Krishnendu Chakrabarty Xinli Gu

Alleviating Scalability Limitation of Accelerator-Based Platforms.

Nasibeh Teimouri Hamed Tabkhi Gunar Schirner

Automatic Retiming of Two-Phase Latch-Based Resilient Circuits.

Huimei Cheng Hsiao-Lun Wang Minghe Zhang Dylan Hand Peter A. Beerel

From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration.

Cheng Zhuo Kassan Unda Yiyu Shi Wei-Kai Shih

Thermal-Aware Modeling and Analysis for a Power Distribution Network Including Through-Silicon-Vias in 3-D ICs.

Weijun Zhu Gang Dong Yintang Yang

A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution.

Leibo Liu Wenping Zhu Shouyi Yin Shaojun Wei

Simultaneous Area and Latency Optimization for Stochastic Circuits by D Flip-Flop Insertion.

Zhijing Li Zhao Chen Yili Zhang Zixin Huang Weikang Qian

Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell Analysis.

Mohamed Ibrahim Krishnendu Chakrabarty Ulf Schlichtmann

An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures.

Alwin Zulehner Alexandru Paler Robert Wille

Automated Dimensioning of Networked Labs-on-Chip.

Andreas Grimmer Werner Haselmayr Robert Wille

Collaborative Power Management Through Knowledge Sharing Among Multiple Devices.

Zhongyuan Tian Zhe Wang Jiang Xu Haoran Li Peng Yang Rafael Kioji Vivas Maeda

Affinity-Driven Modeling and Scheduling for Makespan Optimization in Heterogeneous Multiprocessor Systems.

Kun Cao Junlong Zhou Peijin Cong Liying Li Tongquan Wei Mingsong Chen Shiyan Hu Xiaobo Sharon Hu


Volume 38, Number 6, June 2019
Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning.

Haoyu Yang Jing Su Yi Zou Yuzhe Ma Bei Yu Evangeline F. Y. Young

Scalable Construction of Clock Trees With Useful Skew and High Timing Quality.

Rickard Ewetz Cheng-Kok Koh

Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.

Derong Liu Bei Yu Vinicius S. Livramento Salim Chowdhury Duo Ding Huy Vo Akshay Sharma David Z. Pan

Hardware-Assisted Cross-Generation Prediction of GPUs Under Design.

Kenneth O'Neal Philip Brisk Emily Shriver Michael Kishinevsky

Design and Experimental Evolution of Memristor With Only One VDTA and One Capacitor.

Abdullah Yesil Yunus Babacan Firat Kaçar

A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs).

Xuebing Cao Liyi Xiao Jie Li Rongsheng Zhang Shanshan Liu Jinxiang Wang

An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing.

Satyajit Das Kevin J. M. Martin Davide Rossi Philippe Coussy Luca Benini

Adjusting Learning Rate of Memristor-Based Multilayer Neural Networks via Fuzzy Method.

Shiping Wen Shuixin Xiao Yin Yang Zheng Yan Zhigang Zeng Tingwen Huang

DtCraft: A High-Performance Distributed Execution Engine at Scale.

Tsung-Wei Huang Chun-Xun Lin Martin D. F. Wong

Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths.

Keith A. Campbell Chen-Hsuan Lin Deming Chen

Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators.

Daniele Jahier Pagliari Yves Durand David Coriat Edith Beigné Enrico Macii Massimo Poncino

Logic BIST With Capture-Per-Clock Hybrid Test Points.

Elham K. Moghaddam Nilanjan Mukherjee Janusz Rajski Jedrzej Solecki Jerzy Tyszer Justyna Zawada

Improving Flash Memory Performance and Reliability for Smartphones With I/O Deduplication.

Bo Mao Jindong Zhou Suzhen Wu Hong Jiang Xiao Chen Weijian Yang

Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.

Adib Nahiyan Farimah Farahmandi Prabhat Mishra Domenic Forte Mark M. Tehranipoor

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.

Ricardo Martins Nuno Lourenço Fábio Passos Ricardo Povoa António Canelas Elisenda Roca Rafael Castro-López Javier J. Sieiro Francisco V. Fernández Nuno Horta


Volume 38, Number 5, May 2019
Interpreting Local Variables in AMS Assertions During Simulation.

Antara Ain Pallab Dasgupta

A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures.

Zois-Gerasimos Tasoulas Iraklis Anagnostopoulos Lazaros Papadopoulos Dimitrios Soudris

A User-Centric CPU-GPU Governing Framework for 3-D Mobile Games.

Wei-Ming Chen Sheng-Wei Cheng Pi-Cheng Hsiu

Adaptive 3D-IC TSV Fault Tolerance Structure Generation.

Song Chen Qi Xu Bei Yu

Neural Network Classifier-Based OPC With Imbalanced Training Data.

Suhyeong Choi Seongbo Shim Youngsoo Shin

Effective Logic Synthesis for Threshold Logic Circuit Design.

Augusto Neutzling Jody Maick Matos Alan Mishchenko André Inácio Reis Renato P. Ribas

Scaling Up Modulo Scheduling for High-Level Synthesis.

Leandro de Souza Rosa Christos-Savvas Bouganis Vanderlei Bonato

Are We There Yet? A Study on the State of High-Level Synthesis.

Sakari Lahti Panu Sjovall Jarno Vanne Timo D. Hämäläinen

Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs.

Sugil Lee Daewoo Kim Dong Nguyen Jongeun Lee

Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips.

Sukanta Bhattacharjee Ansuman Banerjee Tsung-Yi Ho Krishnendu Chakrabarty Bhargab B. Bhattacharya

Revive Bad Flash-Memory Pages by HLC Scheme.

Han-Yi Lin Jen-Wei Hsieh

Advanced Simulation of Quantum Computations.

Alwin Zulehner Robert Wille

TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.

Ming Cheng Lixue Xia Zhenhua Zhu Yi Cai Yuan Xie Yu Wang Huazhong Yang

Overcome the GC-Induced Performance Variability in SSD-Based RAIDs With Request Redirection.

Suzhen Wu Haijun Li Bo Mao Xiaoxi Chen Kuan-Ching Li

Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems.

Yuanwen Huang Prabhat Mishra

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking.

Christian Pilato Kaijie Wu Siddharth Garg Ramesh Karri Francesco Regazzoni

MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers.

Xiaowei Xu Feng Lin Wenyao Xu Xin-Wei Yao Yiyu Shi Dewen Zeng Yu Hu


Volume 38, Number 4, April 2019
Bit-Flipping Schemes Upon MLC Flash: Investigation, Implementation, and Evaluation.

Wenhui Zhang Qiang Cao Zhonghai Lu

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug.

Yun Cheng Huawei Li Ying Wang Xiaowei Li

A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs.

Maoxiang Yi Jingchang Bian Tianming Ni Cuiyun Jiang Hao Chang Huaguo Liang

RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code.

Georgios Zacharopoulos Lorenzo Ferretti Emanuele Giaquinta Giovanni Ansaloni Laura Pozzi

Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks.

Francisco E. Rangel-Patino José Ernesto Rayas-Sánchez Andres Viveros-Wacher José Luis Chavez-Hurtado Edgar-Andrei Vega-Ochoa Nagib Hakim

Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis.

Kevin E. Murray Andrea Suardi Vaughn Betz George A. Constantinides

EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations.

Grace Li Zhang Bing Li Yiyu Shi Jiang Hu Ulf Schlichtmann

Efficiently Mapping VLSI Circuits With Simple Cells.

Jody Maick Matos Jordi Carrabina André Inácio Reis

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA.

Shouyi Yin Shibin Tang Xinhan Lin Peng Ouyang Fengbin Tu Leibo Liu Shaojun Wei

STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition.

Nitin Rathi Priyadarshini Panda Kaushik Roy

Reliability Analysis of Mixture Preparation Using Digital Microfluidic Biochips.

Ananya Singla Varsha Agarwal Sudip Roy Arijit Mondal

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.

Guohao Dai Tianhao Huang Yuze Chi Jishen Zhao Guangyu Sun Yongpan Liu Yu Wang Yuan Xie Huazhong Yang

NVQuery: Efficient Query Processing in Nonvolatile Memory.

Mohsen Imani Saransh Gupta Sahil Sharma Tajana Simunic Rosing

A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash Memory.

Yi Wang Mingxu Zhang Xuan Yang Tao Li

Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking.

Anirban Sengupta Deepak Kachave Dipanjan Roy

Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips.

Jack Tang Mohamed Ibrahim Krishnendu Chakrabarty Ramesh Karri


Volume 38, Number 3, March 2019
Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra.

Utkarsh Gupta Priyank Kalla Vikas Rao

Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism.

Gurgen Harutyunyan Samvel K. Shoukourian Yervant Zorian

An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults.

Keewon Cho Young-Woo Lee Sungyoul Seo Sungho Kang

Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption.

Mathieu Da Silva Marie-Lise Flottes Giorgio Di Natale Bruno Rouzeyre

Fast Pareto Front Exploration for Design of Reconfigurable Energy Storage.

Dawon Park Younghyun Kim

Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs.

Jin-Tai Yan

Time-Domain Numerical Simulation of Electronic Circuits and Surface Acoustic Wave Devices Using Their Admittance Parameters.

Jaime Octavio Guerra-Pulido Pablo Roberto Pérez-Alcázar

A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models.

Feilong Zhang Chenkun Wang Fei Lu Qi Chen Cheng Li X. Shawn Wang Daguang Li Albert Z. Wang

2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines.

Scott C. Wolfson Fat D. Ho

An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors.

Sajjad Tamimi Zahra Ebrahimi Behnam Khaleghi Hossein Asadi

A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems.

JuHyung Hong Jeongbin Kim Sangwoo Han Eui-Young Chung

A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach.

Anteneh Gebregiorgis Rajendra Bishnoi Mehdi Baradaran Tahoori

Computer-Aided Design of a Switchable True Time Delay (TTD) Line With Shunt Open-Stubs.

Joydeb Mandal Mrinal Kanti Mandal

Bug Prediction of SystemC Models Using Machine Learning.

Mustafa Efendioglu Alper Sen Yavuz Köroglu

Iterative Search for Reconfigurable Accelerator Blocks With a Compiler in the Loop.

Max Willsey Vincent T. Lee Alvin Cheung Rastislav Bodík Luis Ceze

OPTiC: Optimizing Collaborative CPU-GPU Computing on Mobile Devices With Thermal Constraints.

Siqi Wang Gayathri Ananthanarayanan Tulika Mitra


Volume 38, Number 2, February 2019
Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits.

Xiaowen Wang William H. Robinson

Logic Synthesis for Interpolant Circuit Compaction.

Gianpiero Cabodi Paolo Camurati Marco Palena Paolo Pasini Danilo Vendraminetto

Verification and Synthesis of Clock-Gated Circuits.

Yu-Yun Dai Robert K. Brayton

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering.

Cunxi Yu Maciej J. Ciesielski

LFSR-Based Test Generation for Path Delay Faults.

Irith Pomeranz

Diagnostic Test Generation That Addresses Diagnostic Holes.

Irith Pomeranz

On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries.

Matthew Layne Beckler Ronald D. Blanton

On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains.

Kuen-Jong Lee Bo-Ren Chen Michael Andreas Kochte

Dynamic Approximation of JPEG Hardware.

Farhana Sharmin Snigdha Deepashree Sengupta Jiang Hu Sachin S. Sapatnekar

WCRT Analysis and Evaluation for Sporadic Message-Processing Tasks in Multicore Automotive Gateways.

Guoqi Xie Gang Zeng Ryo Kurachi Hiroaki Takada Zhetao Li Renfa Li Keqin Li

DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography.

Yu-Hsuan Su Yao-Wen Chang

Optimization of Multi-Target Sample Preparation On-Demand With Digital Microfluidic Biochips.

Sudip Poddar Sukanta Bhattacharjee Subhas C. Nandy Krishnendu Chakrabarty Bhargab B. Bhattacharya

Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation.

Bijan Alizadeh Seyyed Reza Sharafinejad

A Temperature-Aware Reliability Enhancement Strategy for 3-D Charge-Trap Flash Memory.

Yi Wang Jiangfan Huang Jing Yang Tao Li

OCMAS: Online Page Clustering for Multibank Scratchpad Memory.

Da-Wei Chang Ing-Chao Lin Yi-Chiao Lin Wen-Zhi Huang

Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack.

Hai Huang Leibo Liu Qihuan Huang Yingjie Chen Shouyi Yin Shaojun Wei

Anti-SAT: Mitigating SAT Attack on Logic Locking.

Yang Xie Ankur Srivastava

TCAD EIC Message: February 2019.

Philip Brisk Suman Chakraborty Claudionor Coelho Abdoulaye Gamatié Swaroop Ghosh Xun Jiao


Volume 38, Number 1, January 2019
TSV Repair Architecture for Clustered Faults.

Jaewon Jang Minho Cheong Sungho Kang

Formal Probabilistic Analysis of Low Latency Approximate Adders.

Amina Qureshi Osman Hasan

Directed Test Generation for Validation of Cache Coherence Protocols.

Yangdi Lyu Xiaoke Qin Mingsong Chen Prabhat Mishra

IC Protection Against JTAG-Based Attacks.

Xuanle Ren Francisco Pimentel Torres Ronald D. Blanton Vítor Grade Tavares

DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG.

Shih-An Hsieh Ying-Hsu Wang Ting-Yu Shen Kuan-Yen Huang Chia-Cheng Pai Tsai-Chieh Chen James Chien-Mo Li

SWIFT: Switch-Level Fault Simulation on GPUs.

Eric Schneider Hans-Joachim Wunderlich

Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression.

Jong Hwan Ko Duckhwan Kim Taesik Na Saibal Mukhopadhyay

Automatic Generation of Peak-Power Traffic for Networks-on-Chip.

Ioannis Seitanidis Chrysostomos Nicopoulos Giorgos Dimitrakopoulos

Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications.

Tianchen Wang Sandeep Kumar Samal Sung Kyu Lim Yiyu Shi

An Analytical Approach for Error PMF Characterization in Approximate Circuits.

Deepashree Sengupta Farhana Sharmin Snigdha Jiang Hu Sachin S. Sapatnekar

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.

Jianlei Yang Xueyan Wang Qiang Zhou Zhaohao Wang Hai Li Yiran Chen Weisheng Zhao

Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.

Luan H. K. Duong Peng Yang Zhifei Wang Yi-Shing Chang Jiang Xu Zhehui Wang Xuanqi Chen

Co-Optimizing Storage Space Utilization and Performance for Key-Value Solid State Drives.

Yen-Ting Chen Ming-Chang Yang Yuan-Hao Chang Tseng-Yi Chen Hsin-Wen Wei Wei-Kuan Shih

Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors.

Fuyang Li Keni Qiu Mengying Zhao Jingtong Hu Yongpan Liu Yong Guan Chun Jason Xue

Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs.

Weichen Liu Juan Yi Mengquan Li Peng Chen Lei Yang